Remove big comments

steps/01-blink-led/sources/cortex-m4-control-registers.h

@@ -1,42 +1,36 @@
 #pragma once
 
-//——————————————————————————————————————————————————————————————————————————————————————————————————————————————————————
-
 #include <stdint.h>
 
-//——————————————————————————————————————————————————————————————————————————————————————————————————————————————————————
 // Peripheral NVIC
-//——————————————————————————————————————————————————————————————————————————————————————————————————————————————————————
 
-//-------------------- Interrupt Set-Enable Registers (idx = 0 ... 7)
+// Interrupt Set-Enable Registers (idx = 0 ... 7)
 #define NVIC_ISER(idx) (* ((const volatile uint32_t *) (0xE000E100 + 0x00 + 4 * (idx))))
 
-//-------------------- Interrupt Clear-Enable Registers (idx = 0 ... 7)
+// Interrupt Clear-Enable Registers (idx = 0 ... 7)
 #define NVIC_ICER(idx) (* ((const volatile uint32_t *) (0xE000E100 + 0x80 + 4 * (idx))))
 
-//-------------------- Interrupt Set-Pending Registers (idx = 0 ... 7)
+// Interrupt Set-Pending Registers (idx = 0 ... 7)
 #define NVIC_ISPR(idx) (* ((const volatile uint32_t *) (0xE000E100 + 0x100 + 4 * (idx))))
 
-//-------------------- Interrupt Clear-Pending Registers (idx = 0 ... 7)
+// Interrupt Clear-Pending Registers (idx = 0 ... 7)
 #define NVIC_ICPR(idx) (* ((const volatile uint32_t *) (0xE000E100 + 0x180 + 4 * (idx))))
 
-//-------------------- Interrupt Active Bit Register (idx = 0 ... 7)
+// Interrupt Active Bit Register (idx = 0 ... 7)
 #define NVIC_IABR(idx) (* ((const volatile uint32_t *) (0xE000E100 + 0x200 + 4 * (idx))))
 
-//-------------------- Interrupt Priority Register (idx = 0 ... 59)
+// Interrupt Priority Register (idx = 0 ... 59)
 #define NVIC_IPR(idx) (* ((const volatile uint32_t *) (0xE000E100 + 0x300 + 4 * (idx))))
 
-//-------------------- Software Trigger Interrupt Register
+// Software Trigger Interrupt Register
 #define NVIC_STIR (* ((volatile uint32_t *) (0xE000E100 + 0xE00)))
 
-  // Field (width: 9 bits): Interrupt ID of the interrupt to trigger, in the range 0-239.
+  // Field (width: 9 bits): Interrupt ID of the interrupt to trigger, in the range 0239.
     inline uint32_t NVIC_STIR_INTID (const uint32_t inValue) { return (inValue & 511) << 0 ; }
 
-//——————————————————————————————————————————————————————————————————————————————————————————————————————————————————————
 // Peripheral SCB
-//——————————————————————————————————————————————————————————————————————————————————————————————————————————————————————
 
-//-------------------- Auxiliary Control Register
+// Auxiliary Control Register
 #define SCB_ACTLR (* ((volatile uint32_t *) (0xE000E000 + 0x8)))
 
   // Boolean field: Disables Interruption Folding
@@ -45,7 +39,7 @@
   // Boolean field: Disabled FPU exception outputs
     static const uint32_t SCB_ACTLR_PFEXCODIS = 1U << 10 ;
 
-  // Boolean field: Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions:
+  // Boolean field: Disables dynamic read allocate mode for WriteBack Write-Allocate memory regions:
     static const uint32_t SCB_ACTLR_DISRAMODE = 1U << 11 ;
 
   // Boolean field: Disables ITM and DWT ATB flush:
@@ -57,22 +51,22 @@
   // Boolean field: Disables the Branch Target Address Cache allocation.
     static const uint32_t SCB_ACTLR_DISBTACALLOC = 1U << 14 ;
 
-  // Boolean field: Disables critical AXI Read-Under-Read.
+  // Boolean field: Disables critical AXI ReadUnder-Read.
     static const uint32_t SCB_ACTLR_DISCRITAXIRUR = 1U << 15 ;
 
-  // Boolean field: Disables dual-issued direct branches.
+  // Boolean field: Disables dualissued direct branches.
     static const uint32_t SCB_ACTLR_DISDI_DB = 1U << 16 ;
 
-  // Boolean field: Disables dual-issued indirect branches.
+  // Boolean field: Disables dualissued indirect branches.
     static const uint32_t SCB_ACTLR_DISDI_IB = 1U << 17 ;
 
-  // Boolean field: Disables dual-issued loads to PC.
+  // Boolean field: Disables dualissued loads to PC.
     static const uint32_t SCB_ACTLR_DISDI_LPC = 1U << 18 ;
 
-  // Boolean field: Disables integer MAC and MUL dual-issued instructions.
+  // Boolean field: Disables integer MAC and MUL dualissued instructions.
     static const uint32_t SCB_ACTLR_DISDI_MAC_MUL = 1U << 19 ;
 
-  // Boolean field: Disables VFP dual-issued instruction.
+  // Boolean field: Disables VFP dualissued instruction.
     static const uint32_t SCB_ACTLR_DISDI_VFP = 1U << 20 ;
 
   // Boolean field: Disables direct branches instructions in channel 1.
@@ -93,7 +87,7 @@
   // Boolean field: Disables dynamic allocation of ADD and SUB instructions:
     static const uint32_t SCB_ACTLR_DISDYNADD = 1U << 26 ;
 
-//-------------------- CPUID Base Register
+// CPUID Base Register
 #define SCB_CPUID (* ((const volatile uint32_t *) (0xE000E000 + 0xD00)))
 
   // Field (width: 4 bits): Revision number, the p value in the rnpn product revision identifier.
@@ -111,7 +105,7 @@
   // Field (width: 8 bits): Implementer code.
     inline uint32_t SCB_CPUID_Implementer (const uint32_t inValue) { return (inValue & 255) << 24 ; }
 
-//-------------------- Interrupt Control and State Register
+// Interrupt Control and State Register
 #define SCB_ICSR (* ((volatile uint32_t *) (0xE000E000 + 0xD04)))
 
   // Field (width: 9 bits): Contains the active exception number.
@@ -126,25 +120,25 @@
   // Boolean field: Interrupt pending flag, excluding NMI and Faults
     static const uint32_t SCB_ICSR_ISRPENDING = 1U << 22 ;
 
-  // Boolean field: SysTick exception clear-pending bit.
+  // Boolean field: SysTick exception clearpending bit.
     static const uint32_t SCB_ICSR_PENDSTCLR = 1U << 25 ;
 
-  // Boolean field: SysTick exception set-pending bit.
+  // Boolean field: SysTick exception setpending bit.
     static const uint32_t SCB_ICSR_PENDSTSET = 1U << 26 ;
 
-  // Boolean field: PendSV clear-pending bit.
+  // Boolean field: PendSV clearpending bit.
     static const uint32_t SCB_ICSR_PENDSVCLR = 1U << 27 ;
 
-  // Boolean field: PendSV set-pending bit.
+  // Boolean field: PendSV setpending bit.
     static const uint32_t SCB_ICSR_PENDSVSET = 1U << 28 ;
 
-  // Boolean field: NMI set-pending bit.
+  // Boolean field: NMI setpending bit.
     static const uint32_t SCB_ICSR_NMIPENDSET = 1U << 31 ;
 
-//-------------------- Vector Table Offset Register
+// Vector Table Offset Register
 #define SCB_VTOR (* ((volatile uint32_t *) (0xE000E000 + 0xD08)))
 
-//-------------------- Application Interrupt and Reset Control Register
+// Application Interrupt and Reset Control Register
 #define SCB_AIRCR (* ((volatile uint32_t *) (0xE000E000 + 0xD0C)))
 
   // Boolean field: System reset request bit setting is implementation defined.
@@ -159,19 +153,19 @@
   // Field (width: 16 bits): Register key. On write, write 0x5FA to VECTKEY, otherwise the write is ignored. Reads as 0xFA05
     inline uint32_t SCB_AIRCR_VECTKEY (const uint32_t inValue) { return (inValue & 65535) << 16 ; }
 
-//-------------------- System Control Register
+// System Control Register
 #define SCB_SCR (* ((volatile uint32_t *) (0xE000E000 + 0xD10)))
 
-  // Boolean field: Indicates sleep-on-exit when returning from Handler mode to Thread mode
+  // Boolean field: Indicates sleepon-exit when returning from Handler mode to Thread mode
     static const uint32_t SCB_SCR_SLEEPONEXIT = 1U << 1 ;
 
-  // Boolean field: Controls whether the processor uses sleep or deep sleep as its low-power mode
+  // Boolean field: Controls whether the processor uses sleep or deep sleep as its lowpower mode
     static const uint32_t SCB_SCR_SLEEPDEEP = 1U << 2 ;
 
   // Boolean field: Send event on pending bit
     static const uint32_t SCB_SCR_SEVONPEND = 1U << 4 ;
 
-//-------------------- Configuration and Control Register
+// Configuration and Control Register
 #define SCB_CCR (* ((volatile uint32_t *) (0xE000E000 + 0xD14)))
 
   // Boolean field: Indicates how the processor enters Thread mode
@@ -186,10 +180,10 @@
   // Boolean field: Enables faulting or halting when the processor executes an SDIF or UDIV instruction with a divisor of 0.
     static const uint32_t SCB_CCR_DIV0_TRP = 1U << 4 ;
 
-  // Boolean field: Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. This applies to the hard fault, NMI, and FAULTMASK escalated handlers.
+  // Boolean field: Enables handlers with priority 1 or -2 to ignore data BusFaults caused by load and store instructions. This applies to the hard fault, NMI, and FAULTMASK escalated handlers.
     static const uint32_t SCB_CCR_BFHFNMIGN = 1U << 8 ;
 
-  // Boolean field: Always reads-as-one. It indicates stack alignment on exception entry is 8-byte aligned.
+  // Boolean field: Always readsas-one. It indicates stack alignment on exception entry is 8-byte aligned.
     static const uint32_t SCB_CCR_STKALIGN = 1U << 9 ;
 
   // Boolean field: Enables L1 data cache.
@@ -198,7 +192,7 @@
   // Boolean field: Enables L1 instruction cache.
     static const uint32_t SCB_CCR_IC = 1U << 17 ;
 
-//-------------------- System Handler Priority Register 1
+// System Handler Priority Register 1
 #define SCB_SHPR1 (* ((volatile uint32_t *) (0xE000E000 + 0xD18)))
 
   // Field (width: 8 bits): Priority of the system handler, MemManage
@@ -210,13 +204,13 @@
   // Field (width: 8 bits): Priority of the system handler, UsageFault
     inline uint32_t SCB_SHPR1_PRI_6 (const uint32_t inValue) { return (inValue & 255) << 16 ; }
 
-//-------------------- System Handler Priority Register 2
+// System Handler Priority Register 2
 #define SCB_SHPR2 (* ((volatile uint32_t *) (0xE000E000 + 0xD1C)))
 
   // Field (width: 8 bits): Priority of the system handler, SVCall
     inline uint32_t SCB_SHPR2_PRI_11 (const uint32_t inValue) { return (inValue & 255) << 24 ; }
 
-//-------------------- System Handler Priority Register 3
+// System Handler Priority Register 3
 #define SCB_SHPR3 (* ((volatile uint32_t *) (0xE000E000 + 0xD20)))
 
   // Field (width: 8 bits): Priority of the system handler, PendSV
@@ -225,7 +219,7 @@
   // Field (width: 8 bits): Priority of the system handler, SysTick
     inline uint32_t SCB_SHPR3_PRI_15 (const uint32_t inValue) { return (inValue & 255) << 24 ; }
 
-//-------------------- System Handler Control and State Register
+// System Handler Control and State Register
 #define SCB_SHCSR (* ((volatile uint32_t *) (0xE000E000 + 0xD24)))
 
   // Boolean field: MemManage exception active bit, reads as 1 if exception is active.
@@ -270,7 +264,7 @@
   // Boolean field: UsageFault enable bit, set to 1 to enable
     static const uint32_t SCB_SHCSR_USGFAULTENA = 1U << 18 ;
 
-//-------------------- MemManage Fault Status Register
+// MemManage Fault Status Register
 #define SCB_CFSR (* ((volatile uint8_t *) (0xE000E000 + 0xD28)))
 
   // Boolean field: Instruction access violation flag
@@ -285,13 +279,13 @@
   // Boolean field: MemManage fault on stacking for exception entry
     static const uint8_t SCB_CFSR_MSTKERR = 1U << 4 ;
 
-  // Boolean field: MemManage fault during floating-point lazy state preservation.
+  // Boolean field: MemManage fault during floatingpoint lazy state preservation.
     static const uint8_t SCB_CFSR_MLSPERR = 1U << 5 ;
 
   // Boolean field: MemManage fault address register valid flag.
     static const uint8_t SCB_CFSR_MMARVALID = 1U << 7 ;
 
-//-------------------- BusFault Status Register
+// BusFault Status Register
 #define SCB_BFSR (* ((volatile uint8_t *) (0xE000E000 + 0xD29)))
 
   // Boolean field: Instruction bus error
@@ -309,13 +303,13 @@
   // Boolean field: BusFault on stacking for exception entry.
     static const uint8_t SCB_BFSR_STKERR = 1U << 4 ;
 
-  // Boolean field: BusFault on floating-point lazy state preservation.
+  // Boolean field: BusFault on floatingpoint lazy state preservation.
     static const uint8_t SCB_BFSR_LSPERR = 1U << 5 ;
 
   // Boolean field: BusFault Address Register valid flag.
     static const uint8_t SCB_BFSR_BFARVALID = 1U << 7 ;
 
-//-------------------- UsageFault Status Register
+// UsageFault Status Register
 #define SCB_UFSR (* ((volatile uint16_t *) (0xE000E000 + 0xD2A)))
 
   // Boolean field: Undefined instruction UsageFault
@@ -336,7 +330,7 @@
   // Boolean field: Divide by zero UsageFault.
     static const uint16_t SCB_UFSR_DIVBYZERO = 1U << 9 ;
 
-//-------------------- HardFault Status Register
+// HardFault Status Register
 #define SCB_HFSR (* ((volatile uint32_t *) (0xE000E000 + 0xD2C)))
 
   // Boolean field: Indicates a BusFault on a vector table read during exception processing.
@@ -348,17 +342,15 @@
   // Boolean field: Reserved for Debug use. When writing to the register, you must write 1 to this bit, otherwise behavior is UNPREDICTABLE.
     static const uint32_t SCB_HFSR_DEBUGEVT = 1U << 31 ;
 
-//-------------------- MemManage Fault Address Register
+// MemManage Fault Address Register
 #define SCB_MMAR (* ((volatile uint32_t *) (0xE000E000 + 0xD34)))
 
-//-------------------- BusFault Address Register
+// BusFault Address Register
 #define SCB_BFAR (* ((volatile uint32_t *) (0xE000E000 + 0xD38)))
 
-//——————————————————————————————————————————————————————————————————————————————————————————————————————————————————————
 // Peripheral SysTick
-//——————————————————————————————————————————————————————————————————————————————————————————————————————————————————————
 
-//-------------------- SysTick Control and Status Register
+// SysTick Control and Status Register
 #define SysTick_CSR (* ((volatile uint32_t *) (0xE000E010 + 0)))
 
   // Boolean field: Enable SysTick Timer
@@ -373,19 +365,19 @@
   // Boolean field: SysTick counted to zero
     static const uint32_t SysTick_CSR_COUNTFLAG = 1U << 16 ;
 
-//-------------------- SysTick Reload Value Register
+// SysTick Reload Value Register
 #define SysTick_RVR (* ((volatile uint32_t *) (0xE000E010 + 0x4)))
 
   // Field (width: 24 bits): Value to auto reload SysTick after reaching zero
     inline uint32_t SysTick_RVR_RELOAD (const uint32_t inValue) { return (inValue & 16777215) << 0 ; }
 
-//-------------------- SysTick Current Value Register
+// SysTick Current Value Register
 #define SysTick_CVR (* ((volatile uint32_t *) (0xE000E010 + 0x8)))
 
   // Field (width: 24 bits): Current value
     inline uint32_t SysTick_CVR_CURRENT (const uint32_t inValue) { return (inValue & 16777215) << 0 ; }
 
-//-------------------- SysTick Calibration Value Register
+// SysTick Calibration Value Register
 #define SysTick_CALIB (* ((const volatile uint32_t *) (0xE000E010 + 0xC)))
 
   // Field (width: 24 bits): Reload value to use for 10ms timing
@@ -397,11 +389,9 @@
   // Boolean field: No Ref
     static const uint32_t SysTick_CALIB_NOREF = 1U << 31 ;
 
-//——————————————————————————————————————————————————————————————————————————————————————————————————————————————————————
 // Peripheral MPU
-//——————————————————————————————————————————————————————————————————————————————————————————————————————————————————————
 
-//-------------------- MPU Type Register
+// MPU Type Register
 #define MPU_TYPE (* ((const volatile uint32_t *) (0xE000ED90 + 0x0)))
 
   // Boolean field: Indicates support for unified or separate instruction and data memory maps.
@@ -413,7 +403,7 @@
   // Field (width: 8 bits): Indicates the number of supported MPU instruction regions. Always contains 0x0: the MPU memory map is unified and is described by the DREGION field.
     inline uint32_t MPU_TYPE_IREGION (const uint32_t inValue) { return (inValue & 255) << 16 ; }
 
-//-------------------- MPU Control Register
+// MPU Control Register
 #define MPU_CTRL (* ((volatile uint32_t *) (0xE000ED90 + 0x4)))
 
   // Boolean field: Enables the optional MPU.
@@ -425,25 +415,25 @@
   // Boolean field: Enables privileged software access to the default memory map.
     static const uint32_t MPU_CTRL_PRIVDEFENA = 1U << 2 ;
 
-//-------------------- MPU Region Number Register
+// MPU Region Number Register
 #define MPU_RNR (* ((volatile uint32_t *) (0xE000ED90 + 0x8)))
 
   // Field (width: 8 bits): Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers.
     inline uint32_t MPU_RNR_REGION (const uint32_t inValue) { return (inValue & 255) << 0 ; }
 
-//-------------------- MPU Region Base Address Register
+// MPU Region Base Address Register
 #define MPU_RBAR (* ((volatile uint32_t *) (0xE000ED90 + 0xC)))
 
   // Field (width: 4 bits): On Write, see the VALID field. On read, specifies the region number.
     inline uint32_t MPU_RBAR_REGION (const uint32_t inValue) { return (inValue & 15) << 0 ; }
 
-  // Boolean field: MPU Region number valid bit. Depending on your implementation, this has the following effect: 0 - either updates the base address for the region specified by MPU_RNR or ignores the value of the REGION field. 1 - either updates the value of the MPU_RNR to the value of the REGION field or updates the base address for the region specified in the REGION field.
+  // Boolean field: MPU Region number valid bit. Depending on your implementation, this has the following effect: 0  either updates the base address for the region specified by MPU_RNR or ignores the value of the REGION field. 1 - either updates the value of the MPU_RNR to the value of the REGION field or updates the base address for the region specified in the REGION field.
     static const uint32_t MPU_RBAR_VALID = 1U << 4 ;
 
   // Field (width: 27 bits): The ADDR field is bits[31:N] of the MPU_RBAR.
     inline uint32_t MPU_RBAR_ADDR (const uint32_t inValue) { return (inValue & 134217727) << 5 ; }
 
-//-------------------- MPU Region Base Attribute and Size Register
+// MPU Region Base Attribute and Size Register
 #define MPU_RASR (* ((volatile uint32_t *) (0xE000ED90 + 0x10)))
 
   // Boolean field: Region enable bit.
@@ -494,29 +484,27 @@
   // Boolean field: Instruction access disable bit
     static const uint32_t MPU_RASR_XN = 1U << 28 ;
 
-//-------------------- Uses (MPU_RNR[7:2]<<2) + 1
+// Uses (MPU_RNR[7:2]<<2) + 1
 #define MPU_RBAR_A1 (* ((volatile uint32_t *) (0xE000ED90 + 0x14)))
 
-//-------------------- Uses (MPU_RNR[7:2]<<2) + 1
+// Uses (MPU_RNR[7:2]<<2) + 1
 #define MPU_RASR_A1 (* ((volatile uint32_t *) (0xE000ED90 + 0x18)))
 
-//-------------------- Uses (MPU_RNR[7:2]<<2) + 2
+// Uses (MPU_RNR[7:2]<<2) + 2
 #define MPU_RBAR_A2 (* ((volatile uint32_t *) (0xE000ED90 + 0x1C)))
 
-//-------------------- Uses (MPU_RNR[7:2]<<2) + 2
+// Uses (MPU_RNR[7:2]<<2) + 2
 #define MPU_RASR_A2 (* ((volatile uint32_t *) (0xE000ED90 + 0x20)))
 
-//-------------------- Uses (MPU_RNR[7:2]<<2) + 3
+// Uses (MPU_RNR[7:2]<<2) + 3
 #define MPU_RBAR_A3 (* ((volatile uint32_t *) (0xE000ED90 + 0x24)))
 
-//-------------------- Uses (MPU_RNR[7:2]<<2) + 3
+// Uses (MPU_RNR[7:2]<<2) + 3
 #define MPU_RASR_A3 (* ((volatile uint32_t *) (0xE000ED90 + 0x28)))
 
-//——————————————————————————————————————————————————————————————————————————————————————————————————————————————————————
 // Peripheral Debug
-//——————————————————————————————————————————————————————————————————————————————————————————————————————————————————————
 
-//-------------------- Debug Fault Status Register
+// Debug Fault Status Register
 #define Debug_DFSR (* ((volatile uint32_t *) (0xE000ED00 + 0x30)))
 
   // Boolean field: Halt request debug event.
@@ -534,7 +522,7 @@
   // Boolean field: An asynchronous exception generated due to the assertion of EDBGRQ.
     static const uint32_t Debug_DFSR_EXTERNAL = 1U << 4 ;
 
-//-------------------- Debug Halting Control and Status Register (on read)
+// Debug Halting Control and Status Register (on read)
 #define Debug_DHCSR_RO (* ((const volatile uint32_t *) (0xE000ED00 + 0xF0)))
 
   // Boolean field: Halting debug enable bit.
@@ -570,7 +558,7 @@
   // Boolean field: Indicates whether the processor has been reset since the last read of DHCSR.
     static const uint32_t Debug_DHCSR_RO_S_RESET_ST = 1U << 25 ;
 
-//-------------------- Debug Halting Control and Status Register (on write)
+// Debug Halting Control and Status Register (on write)
 #define Debug_DHCSR_WO (* ((volatile uint32_t *) (0xE000ED00 + 0xF0)))
 
   // Boolean field: Halting debug enable bit.
@@ -591,19 +579,19 @@
   // Field (width: 16 bits): Debug Key. The value 0xA05F must be written to enable write accesses to bits [15:0], otherwise the write access will be ignored.
     inline uint32_t Debug_DHCSR_WO_S_RESET_ST (const uint32_t inValue) { return (inValue & 65535) << 16 ; }
 
-//-------------------- Debug Core Register Selector Register
+// Debug Core Register Selector Register
 #define Debug_DCRSR (* ((volatile uint32_t *) (0xE000ED00 + 0xF4)))
 
-  // Field (width: 4 bits): Specifies the ARM core register, special-purpose register, or Floating-point extension register, to transfer.
+  // Field (width: 4 bits): Specifies the ARM core register, specialpurpose register, or Floating-point extension register, to transfer.
     inline uint32_t Debug_DCRSR_REGSEL (const uint32_t inValue) { return (inValue & 15) << 0 ; }
 
   // Boolean field: Specifies the access type for the transfer.
     static const uint32_t Debug_DCRSR_REGWnR = 1U << 16 ;
 
-//-------------------- Debug Core Register Data Register
+// Debug Core Register Data Register
 #define Debug_DCRDR (* ((volatile uint32_t *) (0xE000ED00 + 0xF8)))
 
-//-------------------- Debug Exception and Monitor Control Register
+// Debug Exception and Monitor Control Register
 #define Debug_DEMCR (* ((volatile uint32_t *) (0xE000ED00 + 0xFC)))
 
   // Boolean field: Enable Reset Vector Catch. This causes a Local reset to halt a running system.
@@ -645,11 +633,9 @@
   // Boolean field: Global enable for all DWT and ITM features.
     static const uint32_t Debug_DEMCR_TRCENA = 1U << 24 ;
 
-//——————————————————————————————————————————————————————————————————————————————————————————————————————————————————————
 // Peripheral DWT
-//——————————————————————————————————————————————————————————————————————————————————————————————————————————————————————
 
-//-------------------- Control Register
+// Control Register
 #define DWT_CTRL (* ((volatile uint32_t *) (0xE0001000 + 0)))
 
   // Field (width: 4 bits): Number of comparators
@@ -712,68 +698,66 @@
   // Boolean field: enable cycle counter
     static const uint32_t DWT_CTRL_CYCCNTENA = 1U << 0 ;
 
-//-------------------- Cycle Count Register
+// Cycle Count Register
 #define DWT_CYCCNT (* ((volatile uint32_t *) (0xE0001000 + 4)))
 
-//-------------------- CPI Count Register
+// CPI Count Register
 #define DWT_CPICNT (* ((volatile uint32_t *) (0xE0001000 + 8)))
 
-//-------------------- Exception Overhead Count Register
+// Exception Overhead Count Register
 #define DWT_EXCCNT (* ((volatile uint32_t *) (0xE0001000 + 0xC)))
 
-//-------------------- Sleep Count Register
+// Sleep Count Register
 #define DWT_SLEEPCNT (* ((volatile uint32_t *) (0xE0001000 + 0x10)))
 
-//-------------------- LSU Count Register
+// LSU Count Register
 #define DWT_LSUCNT (* ((volatile uint32_t *) (0xE0001000 + 0x14)))
 
-//-------------------- Folded-instruction Count Register
+// Folded-instruction Count Register
 #define DWT_FOLDCNT (* ((volatile uint32_t *) (0xE0001000 + 0x18)))
 
-//-------------------- Program Counter Sample Register
+// Program Counter Sample Register
 #define DWT_PCSR (* ((const volatile uint32_t *) (0xE0001000 + 0x1C)))
 
-//-------------------- Comparator Register 0
+// Comparator Register 0
 #define DWT_COMP0 (* ((volatile uint32_t *) (0xE0001000 + 0x20)))
 
-//-------------------- Mask Register 0
+// Mask Register 0
 #define DWT_MASK0 (* ((volatile uint32_t *) (0xE0001000 + 0x24)))
 
-//-------------------- Function Register 0
+// Function Register 0
 #define DWT_FUNCTION0 (* ((volatile uint32_t *) (0xE0001000 + 0x28)))
 
-//-------------------- Comparator Register 1
+// Comparator Register 1
 #define DWT_COMP1 (* ((volatile uint32_t *) (0xE0001000 + 0x30)))
 
-//-------------------- Mask Register 1
+// Mask Register 1
 #define DWT_MASK1 (* ((volatile uint32_t *) (0xE0001000 + 0x34)))
 
-//-------------------- Function Register 1
+// Function Register 1
 #define DWT_FUNCTION1 (* ((volatile uint32_t *) (0xE0001000 + 0x38)))
 
-//-------------------- Comparator Register 2
+// Comparator Register 2
 #define DWT_COMP2 (* ((volatile uint32_t *) (0xE0001000 + 0x40)))
 
-//-------------------- Mask Register 2
+// Mask Register 2
 #define DWT_MASK2 (* ((volatile uint32_t *) (0xE0001000 + 0x44)))
 
-//-------------------- Function Register 2
+// Function Register 2
 #define DWT_FUNCTION2 (* ((volatile uint32_t *) (0xE0001000 + 0x48)))
 
-//-------------------- Comparator Register 3
+// Comparator Register 3
 #define DWT_COMP3 (* ((volatile uint32_t *) (0xE0001000 + 0x50)))
 
-//-------------------- Mask Register 3
+// Mask Register 3
 #define DWT_MASK3 (* ((volatile uint32_t *) (0xE0001000 + 0x54)))
 
-//-------------------- Function Register 3
+// Function Register 3
 #define DWT_FUNCTION3 (* ((volatile uint32_t *) (0xE0001000 + 0x58)))
 
-//——————————————————————————————————————————————————————————————————————————————————————————————————————————————————————
 // Peripheral SYST
-//——————————————————————————————————————————————————————————————————————————————————————————————————————————————————————
 
-//-------------------- SysTick Control and Status
+// SysTick Control and Status
 #define SYST_CSR (* ((volatile uint32_t *) (0xE000E000 + 0x10)))
 
   // Boolean field: Enable the Counter
@@ -788,13 +772,12 @@
   // Boolean field: Returns 1 if timer counted to 0 since last time this was read
     static const uint32_t SYST_CSR_COUNTFLAG = 1U << 16 ;
 
-//-------------------- SysTick Reload Value Register
+// SysTick Reload Value Register
 #define SYST_RVR (* ((volatile uint32_t *) (0xE000E000 + 0x14)))
 
-//-------------------- SysTick Current Value Register
+// SysTick Current Value Register
 #define SYST_CVR (* ((volatile uint32_t *) (0xE000E000 + 0x18)))
 
-//-------------------- SysTick Calibration Value Register
+// SysTick Calibration Value Register
 #define SYST_CALIB (* ((const volatile uint32_t *) (0xE000E000 + 0x1C)))
 
-//——————————————————————————————————————————————————————————————————————————————————————————————————————————————————————