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@@ -40,10 +40,8 @@ reset.handler: @ Cortex M4 boots with interrupts enabled, in Thread mode
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@--- Software must use an ISB barrier instruction to ensure a write to the CONTROL register
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@ takes effect before the next instruction is executed.
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isb
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-@---------------------------------- Run init routines, interrupt disabled
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- cpsid i @ Disable interrupts
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- bl start.phase2
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- cpsie i @ Enable interrupts
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+@---------------------------------- Run init routines, from SVC handler
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+ svc #0
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@---------------------------------- Run setup, loop
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bl setup.function
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background.task:
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